Recent trends toward high density integrated circuits has increased chip density while simultaneously decreasing both the size of the transistors built on the chip and the gate oxide thicknesses of these transistors.
FIG. 1 schematically shows the relationship between the electrical field (in MV/cm) and gate oxide thickness (in .ANG.) with respect to high voltage logic devices and normal voltage logic devices. As can be seen by FIG. 1, the possibility of a gate oxide breakdown increases with a decrease in gate oxide thickness. To avoid this problem, current designs have reduced device supply voltages (V.sub.DD), which are required to operate a chip. Because a reduction in supply voltage causes a degradation of both device power and speed, however, the thickness of the gate oxide layer in the device must then be reduced as well, to adjust for this lower power and speed.
As is well known, transistor characteristics can be increased by reducing gate oxide thickness while keeping the supply voltage at a constant level. On the other hand, power consumption can be reduced by decreasing the supply voltage while keeping the gate oxide thickness at a constant level. Therefore, the gate oxide thickness must be reduced without causing an oxide breakdown, while maintaining a constant electric field. This is performed in accordance with the so-called "constant electric field scaling law."
Semiconductor memory devices are generally divided into a cell array region and a peripheral region. The cell array region includes a plurality of memory cells in a matrix, and the peripheral region includes circuitry to operate the memory cells.
It is a recent trend in the DRAM or MDL industry, however, that the proportion of the chip area occupied by a cell array is increasing as compared to the chip area occupied by peripheral circuitry. Therefore, if the gate oxide layer is formed to have the same thickness throughout the entire chip, all of the gate oxides in at the cell array region will be subject to suffering from breakdown. Furthermore, since a cell array voltage (V.sub.HDD) that is supplied to the cell array interior exceeds the supply voltage (V.sub.DD), the electric field applied to the cell array interior is increased, which intensifies the possibility of a gate oxide breakdown.
Since the cell density in the cell array region has historically increased four times or each generation of device, a controlled threshold voltage is required to protect against sub-threshold leakage and gate length variation. In other words, a short channel effect margin is required. In addition, it would also be desirable to increase a drain saturation current (I.sub.DSAT) in the peripheral region.
To overcome problems mentioned above, several methods have been proposed. One approach is to increase the doping concentration in the channel region so as to adjust the threshold voltage in consideration of the short channel effect. The increase in the doping concentration, however, decreases the breakdown margin and increases the threshold voltage variation for a given gate length. In other words, gate length margins are reduced.
Another approach is to fabricate the cell array region and peripheral region on different chips, not on a single chip. This method, however, has a disadvantage of increasing process complexity and is not compatible with low cost fabrication.